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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4516DA726
16 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE
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Description Features
Part number
The MC-4516DA726 is a 16,777,216 words by 72 bits synchronous dynamic RAM module on which 9 pieces of
128M SDRAM: PD45128841 are assembled. These modules provide high density and large quantities of memory in a small space without utilizing the surfaceDecoupling capacitors are mounted on power supply line for noise reduction.
mounting technology on the printed circuit board.
* 16,777,216 words by 72 bits organization (ECC type) * Clock frequency and access time from CLK
/CAS latency Clock frequency (MAX.) Access time from CLK (MAX.) 6 ns 6 ns 6 ns 7 ns 6 ns PC100 Registered DIMM Rev. 1.2 Compliant Module type
MC-4516DA726EFC-A80
MC-4516DA726EFC-A10
MC-4516DA726PFC-A80
MC-4516DA726PFC-A10
MC-4516DA726XFC-A80
MC-4516DA726XFC-A10
* Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Pulsed interface * Possible to assert random column address in every cycle * Quad internal banks controlled by BA0 and BA1 (Bank Select) * Programmable burst-length (1, 2, 4, 8 and Full Page) * Programmable wrap sequence (Sequential / Interleave) * Programmable /CAS latency (2, 3)
Document No. E0074N10 (1st edition) (Previous No. M13203EJ8V0DS00) Date Published January 2001 CP(K) Printed in Japan
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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
This product became EOL in March, 2004.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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CL = 3 CL = 2 CL = 3 CL = 2 125 MHz 100 MHz 100 MHz 77 MHz CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 CL = 3 CL = 2 125 MHz 100 MHz 100 MHz 77 MHz 125 MHz 100 MHz 100 MHz 77 MHz
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6 ns 6 ns 7 ns 6 ns 6 ns 6 ns
t uc
7 ns
MC-4516DA726
* Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * All DQs have 10 10 % of series resistor * Single 3.3 V 0.3 V power supply * LVTTL compatible * 4,096 refresh cycles / 64 ms * Burst termination by Burst Stop command and Precharge command * 168-pin dual in-line memory module (Pin pitch = 1.27 mm) * Registered type * Serial PD
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Part number
Ordering Information
Clock frequency (MAX.) 125 MHz 100 MHz 125 MHz 100 MHz 168-pin Dual In-line Memory Module 9 pieces of PD45128841G5 (Rev. E) (Socket Type) Edge connector: Gold plated 38.1 mm height (10.16 mm (400) TSOP (II)) 9 pieces of PD45128841G5 (Rev. P) (10.16 mm (400) TSOP (II)) 9 pieces of PD45128841G5 (Rev. X) (10.16 mm (400) TSOP (II)) Package Mounted devices
MC-4516DA726EFC-A80 MC-4516DA726EFC-A10 MC-4516DA726PFC-A80 MC-4516DA726PFC-A10 MC-4516DA726XFC-A80
MC-4516DA726XFC-A10
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125 MHz 100 MHz
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2
Data Sheet E0074N10
MC-4516DA726
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated) /xxx indicates active low signal.
85 86 87 88 89 90 91 92 93 94 VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 CB4 CB5 VSS NC NC Vcc /CAS DQMB4 DQMB5 NC /RAS VSS A1 A3 A5 A7 A9 BA0 (A13) A11 Vcc CLK1 NC VSS CKE0 NC DQMB6 DQMB7 NC Vcc NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 Vcc VSS DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 CB0 CB1 VSS NC NC Vcc /WE DQMB0 DQMB1 /CS0 NC VSS A0 A2 A4 A6 A8 A10 BA1(A12) Vcc Vcc CLK0 VSS NC /CS2 DQMB2 DQMB3 NC Vcc NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
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95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
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Data Sheet E0074N10
A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A9] BA0 (A13), BA1 (A12) : SDRAM Bank Select DQ0 - DQ63, CB0 - CB7 : Data Inputs/Outputs CLK0 - CLK3 CKE0 WP : Clock Input : Clock Enable Input : Write Protect : Chip Select Input : Row Address Strobe : Column Address Strobe : Write Enable : DQ Mask Enable : Address Input for EEPROM : Serial Data I/O for PD
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/CS0, /CS2 /RAS /WE /CAS DQMB0 - DQMB7 SA0 - SA2 SDA SCL VCC VSS NC REGE
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: Clock Input for PD : Power Supply : Ground : Register / Buffer Enable : No Connection 3
MC-4516DA726
Block Diagram
/RCS0 RDQMB0 RDQMB4
30 pF
10 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
DQ 7 DQM DQ 6 DQ 5 DQ 4 D0 DQ 3 DQ 2 DQ 1 DQ 0
/CS
30 pF DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39
RDQMB5
10
DQ 0 DQM DQ 1 DQ 2 DQ 3 D5 DQ 4 DQ 5 DQ 6 DQ 7
/CS
RDQMB1
15 pF
10
30 pF DQ 7 DQM DQ 6 DQ 5 DQ 4 D1 DQ 3 DQ 2 DQ 1 DQ 0
/CS
10 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47
/CS DQ 0DQM DQ 1 DQ 2 DQ 3 D6 DQ 4 DQ 5 DQ 6 DQ 7
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DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 15 pF CB 0 CB 1 CB 2 CB 3 CB 4 CB 5 CB 6 CB 7
/RCS2 RDQMB2
10 DQ 2 DQM DQ 0 DQ 7 DQ 5 D2 DQ 3 DQ 1 DQ 6 DQ 4
/CS
30 pF DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23
RDQMB3
30 pF DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31
A0 - A9 /RAS /CAS /WE DQMB0, 1, 4, 5 /CS0 REGE LE Register1
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10 DQ 7 DQM DQ 6 DQ 5 DQ 4 D3 DQ 3 DQ 2 DQ 1 DQ 0
/CS
10
CLK0
RDQMB6
CLK : D0,D1,D5 CLK : D2,D3,D6 PLL
30 pF DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55
10
/CS DQ 0 DQM DQ 1 DQ 2 DQ 3 D7 DQ 4 DQ 5 DQ 6 DQ 7
CLK : D4,D7,D8 CLK1 CLK2 CLK3
10 12 pF
CLK : Register 1, Register 2
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RDQMB7
SERIAL PD SCL SDA A0 A1 A2 WP
10
30 pF
DQ 7 DQM DQ 6 DQ 5 DQ 4 D4 DQ 3 DQ 2 DQ 1 DQ 0
/CS
10
DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
DQ 0 DQM DQ 1 DQ 2 DQ 3 D8 DQ 4 DQ 5 DQ 6 DQ 7
/CS
47 k
SA0 SA1 SA2
RA0 - RA9 /RRAS /RCAS /RWE RDQMB0, 1, 4, 5 /RCS0
A0 - A9 : D0 - D8 /RAS : D0 - D8 /CAS : D0 - D8 /WE : D0 - D8
od
VCC VSS A10 - A11, BA0, BA1 RA10, RA11, RBA0, RBA1 RCKE0 CKE0 DQMB2, 3, 6, 7 Register2 /CS2 /RCS2
D0 - D8, Register1, Register2, PLL D0 - D8, Register1, Register2, PLL
C
A10, A11, BA0, BA1 : D0 - D8 CKE : D0 - D8
RDQMB2, 3, 6, 7
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15 pF
15 pF
LE
VCC
10 k
Remarks 1. The value of all resistors of DQs is 10 . 2. D0 - D18: PD45128841 (4M words x 8 bits x 4 banks) 3. REGE VIL: Buffer mode REGE VIH: Register mode 4. Register: HD74ALVC162835 PLL: HD74CDC2509B 4
Data Sheet E0074N10
MC-4516DA726
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 1 ms and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to GND Voltage on input pin relative to GND Short circuit output current Power dissipation Symbol VCC VT IO PD TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 50 12 0 to 70 -55 to +125 Unit V V mA W C C
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Storage temperature
Operating ambient temperature
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA Condition MIN. 3.0 2.0 -0.3 0 TYP. 3.3 MAX. 3.6 VCC + 0.3 +0.8 70 Unit V V V C
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance
Data input/output capacitance
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Symbol CI1 CI2 CI3 CI4 CI5 CI/O Test condition A0 - A11, BA0 (A13), BA1 (A12), /RAS, /CAS, /WE CLK0 CKE0 /CS0, /CS2 DQMB0 - DQMB7 DQ0 - DQ63, CB0 - CB7
Data Sheet E0074N10
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MIN. 4 15 4 4 3 5
TYP.
MAX. 10 25 10 10 10
Unit pF
t uc
13 pF
5
MC-4516DA726
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter Operating current Symbol ICC1 Burst length = 1 tRC tRC (MIN.), IO = 0 mA /CAS latency = 3 Test condition /CAS latency = 2 Grade -A80 -A10 -A80 -A10 Precharge standby current in power down mode ICC2P ICC2PS ICC2N CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. ICC2NS CKE VIH (MIN.), tCK = , Input signals are stable. ICC3P ICC3PS ICC3N CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. 260 295 116 520 mA mA 152 MIN. MAX. 1,200 1,200 1,200 1,200 259 89 430 mA mA Unit Notes mA 1
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non power down mode Active standby current in power down mode Active standby current in non power down mode Operating current (Burst mode) Self refresh current Input leakage current Output leakage current High level output voltage Low level output voltage
Precharge standby current in
CBR (Auto) Refresh current
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.).
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ICC3NS ICC4 ICC5 ICC6 II (L) IO (L) VOH VOL
CKE VIH (MIN.), tCK = , Input signals are stable. tCK tCK (MIN.), IO = 0 mA /CAS latency = 2 -A80 -A10 -A80 -A10 -A80 -A10 -A80 -A10
1,380 1,155 1,605 1,425 2,370 2,370 2,370 2,370 268 -10 -1.5 2.4 +10 +1.5
mA
2
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tRC tRC (MIN.) CKE 0.2 V DOUT is disabled, VO = 0 to 3.6 V IO = -4.0 mA IO = +4.0 mA
Data Sheet E0074N10
/CAS latency = 3
/CAS latency = 2
mA
3
VI = 0 to 3.6 V, All other pins not under test = 0 V
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/CAS latency = 3
mA
A A
V
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0.4 V
6
MC-4516DA726
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Test Conditions
Parameter AC high level input voltage / low level input voltage Input timing measurement reference level Transition time (Input rise and fall time) Output timing measurement reference level Value 2.4 / 0.4 1.4 1 1.4 Unit V V ns V
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tCK tCH CLK 2.4 V 1.4 V 0.4 V tSETUP tHOLD 2.4 V 1.4 V 0.4 V tAC tOH tCL
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Input Output
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Data Sheet E0074N10
od t uc
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MC-4516DA726
Synchronous Characteristics
Parameter Symbol MIN. Clock cycle time
/CAS latency = 3 /CAS latency = 2
-A80 MAX. (125 MHz) (100 MHz) 6 6 50 40 125 60 50 40 3 3 0 6 6 3 3 2 1 2 1 2 1 2 2 MIN. 10 13
-A10 MAX. (100 MHz) (77 MHz) 6 7 100 60
Unit
Note
tCK3 tCK2 tAC3 tAC2
8 10
ns ns ns ns MHz % ns ns ns 1 1 1 1
Access time from CLK
/CAS latency = 3 /CAS latency = 2
Input clock frequency Input CLK duty cycle Data-out hold time
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Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time DQMB7) setup time DQMB7) hold time
/CAS latency = 3 /CAS latency = 2
tOH3 tOH2 tLZ
3 3 0 3 3 2 1 2 1 2 1
Data-out low-impedance time Data-out high- impedance time
/CAS latency = 3 /CAS latency = 2
tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH
6 7
ns ns ns ns ns ns ns ns ns ns
CKE setup time (Power down exit)
Command (/CS0, /CS2, /RAS, /CAS, /WE, DQMB0 -
Command (/CS0, /CS2, /RAS, /CAS, /WE, DQMB0 -
Note 1. Output load
Output
Remark These specifications are applied to the monolithic device.
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tCKSP tCMS 2 2 tCMH 1
Z = 50 50 pF
Data Sheet E0074N10
1
ns
od t uc
8
MC-4516DA726
Asynchronous Characteristics
Parameter Symbol MIN. REF to REF/ACT command period ACT to PRE command period PRE to ACT command period Delay time ACT to READ/WRITE command ACT(one) to ACT(another) command period Data-in to PRE command period Data-in to ACT(REF) command period (Auto precharge)
/CAS latency = 3 /CAS latency = 2
-A 80 MAX. MIN. 70 120,000 50 20 20 20
-A 10 MAX.
Unit
Note
tRC tRAS tRP tRCD tRRD tDPL tDAL3 tDAL2 tRSC tT tREF
70 48 20 20 16 -1CLK+8 20 20 2 0.5 30 64
ns 120,000 ns ns ns ns ns ns ns CLK 30 64 ns ms
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Transition time
-1CLK+10 20 20 2 1
Mode register set cycle time
Refresh time (4,096 refresh cycles)
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Data Sheet E0074N10
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9
MC-4516DA726
Serial PD
Byte No. 0 1 2 3 4 5 6 7 8 9 Function Described Defines the number of bytes written into serial PD memory Total number of bytes of serial PD memory Fundamental memory type Number of rows Number of columns Number of banks Data width Hex 80H 08H 04H 0CH 0AH 01H 48H 00H 01H -A80 -A10 -A80 -A10 80H A0H 60H 60H 02H 80H 08H 08H 01H 8FH 04H Bit 7 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 Bit 6 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 Bit 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bit 3 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 Bit 2 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 Bit 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 Bit 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 20 ns 20 ns 10 ns 13 ns 6 ns 7 ns
(1/2)
Notes 128 bytes 256 bytes SDRAM 12 rows 10 columns 1 bank 72 bits 0 LVTTL 8 ns 10 ns 6 ns 6 ns ECC Normal x8 x8 1 clock 1, 2, 4, 8, F 4 banks 2, 3 0 0 Registered
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10 11 12 13 14 15 16 17 18 19 20 21 22 23 SDRAM width 24 25-26 27 tRP(MIN.) 28 tRRD(MIN.) 29 tRCD(MIN.) 30 tRAS(MIN.) 31
Data width (continued) Voltage interface CL = 3 Cycle time
CL = 3 Access time
DIMM configuration type Refresh rate/type
Error checking SDRAM width Minimum clock delay Burst length supported
Number of banks on each SDRAM /CAS latency supported /CS latency supported
/WE latency supported
SDRAM module attributes
SDRAM device attributes : General CL = 2 Cycle time
CL = 2 Access time
Module bank density
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-A80 -A10 -A80 -A10 -A80 -A10 -A80 -A10 -A80 -A10 -A80 -A10
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0 0 06H 0 0 01H 0 0 01H 0 0 1FH 0 0 0EH 0 0 A0H 1 0 D0H 60H 1 1 0 1 70H 00H 0 1 0 0 14H 0 0 14H 10H 14H 14H 14H 30H 32H 20H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data Sheet E0074N10
0
0 0
0
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1 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 0 1 0 0 0 0 0
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0 0 16 ns 0 0 20 ns 0 0 20 ns 0 0 20 ns 0 0 48 ns 1 0 50 ns 0 0 128M bytes
10
MC-4516DA726
(2/2)
Byte No. 32 33 34 35 36-61 Function Described Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Hex 20H 10H 20H 10H 00H SPD revision 12H -A80 -A10 21H 87H Bit 7 0 0 0 0 0 0 0 1 Bit 6 0 0 0 0 0 0 0 0 Bit 5 1 0 1 0 0 0 1 0 Bit 4 0 1 0 1 0 1 0 0 Bit 3 0 0 0 0 0 0 0 0 Bit 2 0 0 0 0 0 0 0 1 Bit 1 0 0 0 0 0 1 0 1 Bit 0 0 0 0 0 0 0 1 1 1.2 A 2 ns 1 ns 2 ns 1 ns Notes
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62 63 64-71 72 73-90 91 93-94 95-98 99-125 126 127 Mfg specific
Checksum for bytes 0 - 62
Manufacture's JEDEC ID code Manufacturing location
Manufacture's P/N Revision Code
Manufacturing date Assembly serial number
Intel specification frequency Intel specification /CAS latency support
Timing Chart
Refer to the PD45128441, 45128841, 45128163 Data sheet (E0031N).
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64H -A80 -A10 87H 85H
0 1 1
1 0 0
1 0 0
0 0 0
0 0 0
1 1 1
0 1 0
0 1 1
100 MHz
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Data Sheet E0074N10
od t uc
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MC-4516DA726
Package Drawing
168-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B) M1 (AREA B) Y Z N
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R M2 (AREA A) J I
Q L A H K C G D A1 (AREA A) B S
(OPTIONAL HOLES)
M
U T
B
E
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detail of A part W V X
ITEM A A1 B C D D1 D2 E G H I J K L M M1 M2 N P
MILLIMETERS 133.35 133.350.13 11.43 36.83 6.35 2.0 3.125 54.61 6.35 1.27 (T.P.) 8.89 24.495 42.18 17.78 38.10.13 18.32 19.78 4.0 MAX. 1.0 R2.0 4.00.10
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Data Sheet E0074N10
detail of B part D2
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P D1
t uc
Q R S T U V
3.0
1.270.1 4.0 MIN. 0.20.15 1.00.05
W X Y Z
2.540.10 3.0 MIN. 3.0 MIN.
M168S-50A106
12
MC-4516DA726
[MEMO]
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Data Sheet E0074N10
od t uc
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MC-4516DA726
[MEMO]
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Data Sheet E0074N10
MC-4516DA726
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3
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2 Note:
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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Data Sheet E0074N10
od
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15
MC-4516DA726
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
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* The information in this document is current as of September, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all products and/or types are available in every country. Please check with an Elpida Memory, Inc. for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document. * Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of Elpida semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * Elpida semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine Elpida's willingness to support a given application. (Note) (1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned subsidiaries. (2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or for Elpida (as defined above).
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M8E 00. 4

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